/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * include/linux/mfd/serdes/gpio.h -- GPIO for different serdes chip
 *
 * Copyright (c) 2023-2028 Rockchip Electronics Co., Ltd.
 *
 * Author: luowei <lw@rock-chips.com>
 *
 */

#ifndef __MFD_SERDES_ROHM_BU18TL82_H__
#define __MFD_SERDES_ROHM_BU18TL82_H__

#define BU18TL82_REG_SWRST_INTERNAL 0x0011
#define BU18TL82_REG_SWRST_MIPIRX 0x0012

#define BU18TL82_REG_SWRST_INTERNAL 0x0011
#define BU18TL82_REG_SWRST_MIPIRX 0x0012

#define BU18TL82_BLOCK_EN_MIPIRX0 0x0013	//h [0] 1’b0
#define BU18TL82_BLOCK_EN_LVDSRX0 0x0013	//h [1] 1’b0
#define BU18TL82_BLOCK_EN_CLLTX0 0x0013	//h [3] 1’b0
#define BU18TL82_BLOCK_EN_VPLL0 0x0013	//h [4] 1’b0
#define BU18TL82_BLOCK_EN_SSCG0 0x0013	//h [5] 1’b0
#define BU18TL82_BLOCK_EN_MIPIRX1 0x0014	//h [0] 1’b0
#define BU18TL82_BLOCK_EN_LVDSRX1 0x0014	//h [1] 1’b0
#define BU18TL82_BLOCK_EN_CLLTX1 0x0014	//h [3] 1’b0
#define BU18TL82_BLOCK_EN_VPLL1 0x0014	//h [4] 1’b0
#define BU18TL82_BLOCK_EN_SSCG1 0x0014	//h [5] 1’b0

/*gpio register for driver/direction/pull-down*/
#define BU18TL82_IO_SW_GPIO0 0x002A	//h [2:1] 2’b00
#define BU18TL82_IO_OEN_GPIO0 0x002A	//h [3] 1’b1
#define BU18TL82_IO_PDEN_GPIO0 0x002A	//h [4] 1’b1
#define BU18TL82_IO_SW_GPIO1 0x002D	//h [2:1] 2’b00
#define BU18TL82_IO_OEN_GPIO1 0x002D	//h [3] 1’b1
#define BU18TL82_IO_PDEN_GPIO1 0x002D	//h [4] 1’b1
#define BU18TL82_IO_SW_GPIO2 0x0030	//h [2:1] 2’b00
#define BU18TL82_IO_OEN_GPIO2 0x0030	//h [3] 1’b1
#define BU18TL82_IO_PDEN_GPIO2 0x0030	//h [4] 1’b1
#define BU18TL82_IO_SW_GPIO3 0x0033	//h [2:1] 2’b00
#define BU18TL82_IO_OEN_GPIO3 0x0033	//h [3] 1’b1
#define BU18TL82_IO_PDEN_GPIO3 0x0033	//h [4] 1’b1
#define BU18TL82_IO_SW_GPIO4 0x0036	//h [2:1] 2’b00
#define BU18TL82_IO_OEN_GPIO4 0x0036	//h [3] 1’b1
#define BU18TL82_IO_PDEN_GPIO4 0x0036	//h [4] 1’b1
#define BU18TL82_IO_SW_GPIO5 0x0039	//h [2:1] 2’b00
#define BU18TL82_IO_OEN_GPIO5 0x0039	//h [3] 1’b1
#define BU18TL82_IO_PDEN_GPIO5 0x0039	//h [4] 1’b1
#define BU18TL82_IO_SW_GPIO6 0x003C	//h [2:1] 2’b00
#define BU18TL82_IO_OEN_GPIO6 0x003C	//h [3] 1’b1
#define BU18TL82_IO_PDEN_GPIO6 0x003C	//h [4] 1’b1
#define BU18TL82_IO_SW_GPIO7 0x003F	//h [2:1] 2’b00
#define BU18TL82_IO_OEN_GPIO7 0x003F	//h [3] 1’b1
#define BU18TL82_IO_PDEN_GPIO7 0x003F	//h [4] 1’b1

/*
 * gpio register for define connection with des gpiox.
 * 11bits such as 0x002c:002b=[b2..b0 b7...b0]
 *
 * default value:
 * ser gpio0-->des gpio0
 * ser gpio1-->des gpio1
 * ser gpio2-->des gpio2
 * ser gpio3-->des gpio3
 */
#define BU18TL82_GPIO_SEL0_HIGH 0x002C	//h [2:0],
#define BU18TL82_GPIO_SEL0_LOW 0x002B	//h [7:0] 11’h002
#define BU18TL82_GPIO_SEL1_HIGH 0x002F	//h [2:0],
#define BU18TL82_GPIO_SEL1_LOW 0x002E	//h [7:0] 11’h003
#define BU18TL82_GPIO_SEL2_HIGH 0x0032	//h [2:0],
#define BU18TL82_GPIO_SEL2_LOW 0x0031	//h [7:0] 11’h004
#define BU18TL82_GPIO_SEL3_HIGH 0x0035	//h [2:0],
#define BU18TL82_GPIO_SEL3_LOW 0x0034	//h [7:0] 11’h005
#define BU18TL82_GPIO_SEL4_HIGH 0x0038	//h [2:0],
#define BU18TL82_GPIO_SEL4_LOW 0x0037	//h [7:0] 11’h006
#define BU18TL82_GPIO_SEL5_HIGH 0x003B	//h [2:0],
#define BU18TL82_GPIO_SEL5_LOW 0x003A	//h [7:0] 11’h007
/*datasheet about gpio6/7 need modify*/
#define BU18TL82_GPIO_SEL6_LOW 0x003E	//h [2:0],
#define BU18TL82_GPIO_SEL6_HIGH 0x003D	//h [7:0] 11’h008
#define BU18TL82_GPIO_SEL7_LOW 0x0041	//h [2:0],
#define BU18TL82_GPIO_SEL7_HIGH 0x0040	//h [7:0] 11’h009

/*gpio register for define bu18tl82 gpio pin, and gpio0 to gpio0 default*/
#define BU18TL82_FCCTX0_SEL_GPI0 0x02A7	//h [4:0] 5’h02
#define BU18TL82_FCCTX0_SEL_GPI1 0x02A8	//h [4:0] 5’h03
#define BU18TL82_FCCTX0_SEL_GPI2 0x02A9	//h [4:0] 5’h04
#define BU18TL82_FCCTX0_SEL_GPI3 0x02AA	//h [4:0] 5’h05
#define BU18TL82_FCCTX0_SEL_GPI4 0x02AB	//h [4:0] 5’h06
#define BU18TL82_FCCTX0_SEL_GPI5 0x02AC	//h [4:0] 5’h07
#define BU18TL82_FCCTX0_SEL_GPI6 0x02AD	//h [4:0] 5’h08
#define BU18TL82_FCCTX0_SEL_GPI7 0x02AE	//h [4:0] 5’h09
#define BU18TL82_CLLTX0_SEL_GPI0 0x02AF	//h [4:0] 5’h04
#define BU18TL82_CLLTX0_SEL_GPI1 0x02B0	//h [4:0] 5’h05

#define BU18TL82_FCCTX1_SEL_GPI0 0x03A7	//h [4:0] 5’h02
#define BU18TL82_FCCTX1_SEL_GPI1 0x03A8	//h [4:0] 5’h03
#define BU18TL82_FCCTX1_SEL_GPI2 0x03A9	//h [4:0] 5’h04
#define BU18TL82_FCCTX1_SEL_GPI3 0x03AA	//h [4:0] 5’h05
#define BU18TL82_FCCTX1_SEL_GPI4 0x03AB	//h [4:0] 5’h06
#define BU18TL82_FCCTX1_SEL_GPI5 0x03AC	//h [4:0] 5’h07
#define BU18TL82_FCCTX1_SEL_GPI6 0x03AD	//h [4:0] 5’h08
#define BU18TL82_FCCTX1_SEL_GPI7 0x03AE	//h [4:0] 5’h09
#define BU18TL82_CLLTX1_SEL_GPI0 0x03AF	//h [4:0] 5’h04
#define BU18TL82_CLLTX1_SEL_GPI1 0x03B0	//h [4:0] 5’h05

/*write 1'b0 to this register to clear all isr register value8*/
#define BU18TL82_ISR_CLEAR_ALL 0x0105	//h[0]

#define BU18TL82_ISR_BCCDES0_ERR_CRC 0x0131			//h [3] 1’b0
#define BU18TL82_ISR_BCCRX0_STATUS_NEAR_LOST 0x0131	//h[7]
#define BU18TL82_ISR_BCCDES1_ERR_CRC 0x0132			//h [3] 1’b0
#define BU18TL82_ISR_BCCRX1_STATUS_NEAR_LOST 0x0132	//h[7]
#define BU18TL82_ISR_MIPIRX0_SOT_ERR 0x0133			//h[0]
#define BU18TL82_ISR_MIPIRX0_SOT_SYNC_ERR 0x0133	//h[1]
#define BU18TL82_ISR_MIPIRX0_EOT_SYNC_ERR 0x0133	//h[2]
#define BU18TL82_ISR_MIPIRX0_ECC1BIT_ERR 0x0134		//h[0]
#define BU18TL82_ISR_MIPIRX0_ECCMULT_ERR 0x0134		//h[1]
#define BU18TL82_ISR_MIPIRX0_CRC_ERR 0x0134			//h[2]
#define BU18TL82_ISR_MIPIRX1_SOT_ERR 0x0135			//h[0]
#define BU18TL82_ISR_MIPIRX1_SOT_SYNC_ERR 0x0135	//h[1]
#define BU18TL82_ISR_MIPIRX1_EOT_SYNC_ERR 0x0135	//h[2]
#define BU18TL82_ISR_MIPIRX1_ECC1BIT_ERR 0x0136		//h[0]
#define BU18TL82_ISR_MIPIRX1_ECCMULT_ERR 0x0136		//h[1]
#define BU18TL82_ISR_MIPIRX1_CRC_ERR 0x0136			//h[2]
#define BU18TL82_ISR_LVDSRX0_V_TOTAL_MAX_ERR 0x0137		//h[0]
#define BU18TL82_ISR_LVDSRX0_V_TOTAL_MIN_ERR 0x0137		//h[1]
#define BU18TL82_ISR_LVDSRX0_V_ACTIVE_MAX_ERR 0x0137	//h[2]
#define BU18TL82_ISR_LVDSRX0_V_ACTIVE_MIN_ERR 0x0137	//h[3]
#define BU18TL82_ISR_LVDSRX0_H_TOTAL_MAX_ERR 0x0137		//h[4]
#define BU18TL82_ISR_LVDSRX0_H_TOTAL_MIN_ERR 0x0137		//h[5]
#define BU18TL82_ISR_LVDSRX0_H_ACTIVE_MAX_ERR 0x0137	//h[6]
#define BU18TL82_ISR_LVDSRX0_H_ACTIVE_MIN_ERR 0x0137	//h[7]
#define BU18TL82_ISR_LVDSRX1_V_TOTAL_MAX_ERR 0x0138		//h[0]
#define BU18TL82_ISR_LVDSRX1_V_TOTAL_MIN_ERR 0x0138		//h[1]
#define BU18TL82_ISR_LVDSRX1_V_ACTIVE_MAX_ERR 0x0138	//h[2]
#define BU18TL82_ISR_LVDSRX1_V_ACTIVE_MIN_ERR 0x0138	//h[3]
#define BU18TL82_ISR_LVDSRX1_H_TOTAL_MAX_ERR 0x0138		//h[4]
#define BU18TL82_ISR_LVDSRX1_H_TOTAL_MIN_ERR 0x0138		//h[5]
#define BU18TL82_ISR_LVDSRX1_H_ACTIVE_MAX_ERR 0x0138	//h[6]
#define BU18TL82_ISR_LVDSRX1_H_ACTIVE_MIN_ERR 0x0138	//h[7]
#define BU18TL82_ISR_IO_STUCK_GPIO0 0x0139	//h[0]
#define BU18TL82_ISR_IO_STUCK_GPIO1 0x0139	//h[1]
#define BU18TL82_ISR_IO_STUCK_GPIO2 0x0139	//h[2]
#define BU18TL82_ISR_IO_STUCK_GPIO3 0x0139	//h[3]
#define BU18TL82_ISR_IO_STUCK_GPIO4 0x0139	//h[4]
#define BU18TL82_ISR_IO_STUCK_GPIO5 0x0139	//h[5]
#define BU18TL82_ISR_IO_STUCK_GPIO6 0x0139	//h[6]
#define BU18TL82_ISR_IO_STUCK_GPIO7 0x0139	//h[7]
#define BU18TL82_ISR_IO_STUCK_IRQ 0x013a	//h[1]
#define BU18TL82_ISR_IDS_UNSTABLE 0x013a	//h [7] 1’b0
#define BU18TL82_ISR_I2C_A_TIMEOUT 0x013b	//h [0] 1’b0
#define BU18TL82_ISR_I2C_A_XMIT_ERR 0x013b	//h [1] 1’b0
#define BU18TL82_ISR_I2C_B_TIMEOUT 0x013c	//h [0] 1’b0
#define BU18TL82_ISR_I2C_B_XMIT_ERR 0x013c	//h [1] 1’b0
#define BU18TL82_ISR_REGCRC_ERR_PAGE0 0x013d	//h[0]
#define BU18TL82_ISR_REGCRC_ERR_PAGE1 0x013d	//h[1]
#define BU18TL82_ISR_REGCRC_ERR_PAGE2 0x013d	//h[2]
#define BU18TL82_ISR_REGCRC_ERR_PAGE3 0x013d	//h[3]
#define BU18TL82_ISR_REGCRC_ERR_PAGE4 0x013d	//h[4]
#define BU18TL82_ISR_REGCRC_ERR_PAGE5 0x013d	//h[5]
#define BU18TL82_ISR_CLKDETECT_CLKIN0_STOP 0x013e	//h [0] 1’b0
#define BU18TL82_ISR_CLKDETECT_CLKIN0_UNLOCK 0x013e	//h [1] 1’b0
#define BU18TL82_ISR_CLKDETECT_OSC_STOP 0x013e		//h [4] 1’b0
#define BU18TL82_ISR_CLKDETECT_OSC_UNLOCK 0x013e	//h [5] 1’b0
#define BU18TL82_ISR_CLKDETECT_CLKIN1_STOP 0x013f	//h [0] 1’b0
#define BU18TL82_ISR_CLKDETECT_CLKIN1_UNLOCK 0x013f	//h [1] 1’b0
#define BU18TL82_ISR_CLKDETECT_LVDSRX0_STOP 0x0140		//h [0] 1’b0
#define BU18TL82_ISR_CLKDETECT_LVDSRX0_UNLOCK 0x0140	//h [1] 1’b0
#define BU18TL82_ISR_CLKDETECT_MIPIRX0_STOP 0x0140		//h [4] 1’b0
#define BU18TL82_ISR_CLKDETECT_MIPIRX0_UNLOCK 0x0140	//h [5] 1’b0
#define BU18TL82_ISR_CLKDETECT_LVDSRX1_STOP 0x0141		//h [0] 1’b0
#define BU18TL82_ISR_CLKDETECT_LVDSRX1_UNLOCK 0x0141	//h [1] 1’b0
#define BU18TL82_ISR_CLKDETECT_MIPIRX1_STOP 0x0141		//h [4] 1’b0
#define BU18TL82_ISR_CLKDETECT_MIPIRX1_UNLOCK 0x0141	//h [5] 1’b0
#define BU18TL82_ISR_CLKDETECT_CLLTX0_SCLK_STOP 0x0142		//h [0] 1’b0
#define BU18TL82_ISR_CLKDETECT_CLLTX0_SCLK_UNLOCK 0x0142	//h [1] 1’b0
#define BU18TL82_ISR_CLKDETECT_CLLTX0_PLLREF_STOP 0x0142	//h [4] 1’b0
#define BU18TL82_ISR_CLKDETECT_CLLTX0_PLLREF_UNLOCK 0x0142	//h [5] 1’b0
#define BU18TL82_ISR_CLKDETECT_CLLTX1_SCLK_STOP 0x0143		//h [0] 1’b0
#define BU18TL82_ISR_CLKDETECT_CLLTX1_SCLK_UNLOCK 0x0143	//h [1] 1’b0
#define BU18TL82_ISR_CLKDETECT_CLLTX1_PLLREF_STOP 0x0143	//h [4] 1’b0
#define BU18TL82_ISR_CLKDETECT_CLLTX1_PLLREF_UNLOCK 0x0143	//h [5] 1’b0
#define BU18TL82_ISR_STATUS_RX0_ISR00 0x0149	//h [0] 1’b0
#define BU18TL82_ISR_STATUS_RX0_ISR01 0x0149	//h [1] 1’b0
#define BU18TL82_ISR_STATUS_RX0_ISR02 0x0149	//h [2] 1’b0
#define BU18TL82_ISR_STATUS_RX0_ISR03 0x0149	//h [3] 1’b0
#define BU18TL82_ISR_STATUS_RX0_ISR04 0x0149	//h [4] 1’b0
#define BU18TL82_ISR_STATUS_RX0_ISR05 0x0149	//h [5] 1’b0
#define BU18TL82_ISR_STATUS_RX0_ISR06 0x0149	//h [6] 1’b0
#define BU18TL82_ISR_STATUS_RX0_ISR07 0x0149	//h [7] 1’b0
#define BU18TL82_ISR_STATUS_RX0_ISR08 0x014a	//h [0] 1’b0
#define BU18TL82_ISR_STATUS_RX0_ISR09 0x014a	//h [1] 1’b0
#define BU18TL82_ISR_STATUS_RX0_ISR10 0x014a	//h [2] 1’b0

#define BU18TL82_IEN_BCCDES0_ERR_CRC 0x0109			//h [3] 1’b0
#define BU18TL82_IEN_BCCRX0_STATUS_NEAR_LOST 0x0109	//h[7]
#define BU18TL82_IEN_BCCDES1_ERR_CRC 0x010A			//h [3] 1’b0
#define BU18TL82_IEN_BCCRX1_STATUS_NEAR_LOST 0x010A	//h[7]
#define BU18TL82_IEN_MIPIRX0_SOT_ERR 0x010B			//h[0]
#define BU18TL82_IEN_MIPIRX0_SOT_SYNC_ERR 0x010B	//h[1]
#define BU18TL82_IEN_MIPIRX0_EOT_SYNC_ERR 0x010B	//h[2]
#define BU18TL82_IEN_MIPIRX0_ECC1BIT_ERR 0x010C		//h[0]
#define BU18TL82_IEN_MIPIRX0_ECCMULT_ERR 0x010C		//h[1]
#define BU18TL82_IEN_MIPIRX0_CRC_ERR 0x010C			//h[2]
#define BU18TL82_IEN_MIPIRX1_SOT_ERR 0x010D			//h[0]
#define BU18TL82_IEN_MIPIRX1_SOT_SYNC_ERR 0x010D	//h[1]
#define BU18TL82_IEN_MIPIRX1_EOT_SYNC_ERR 0x010D	//h[2]
#define BU18TL82_IEN_MIPIRX1_ECC1BIT_ERR 0x010E		//h[0]
#define BU18TL82_IEN_MIPIRX1_ECCMULT_ERR 0x010E		//h[1]
#define BU18TL82_IEN_MIPIRX1_CRC_ERR 0x010E			//h[2]
#define BU18TL82_IEN_LVDSRX0_V_TOTAL_MAX_ERR 0x010F		//h[0]
#define BU18TL82_IEN_LVDSRX0_V_TOTAL_MIN_ERR 0x010F		//h[1]
#define BU18TL82_IEN_LVDSRX0_V_ACTIVE_MAX_ERR 0x010F	//h[2]
#define BU18TL82_IEN_LVDSRX0_V_ACTIVE_MIN_ERR 0x010F	//h[3]
#define BU18TL82_IEN_LVDSRX0_H_TOTAL_MAX_ERR 0x010F		//h[4]
#define BU18TL82_IEN_LVDSRX0_H_TOTAL_MIN_ERR 0x010F		//h[5]
#define BU18TL82_IEN_LVDSRX0_H_ACTIVE_MAX_ERR 0x010F	//h[6]
#define BU18TL82_IEN_LVDSRX0_H_ACTIVE_MIN_ERR 0x010F	//h[7]
#define BU18TL82_IEN_LVDSRX1_V_TOTAL_MAX_ERR 0x0110		//h[0]
#define BU18TL82_IEN_LVDSRX1_V_TOTAL_MIN_ERR 0x0110		//h[1]
#define BU18TL82_IEN_LVDSRX1_V_ACTIVE_MAX_ERR 0x0110	//h[2]
#define BU18TL82_IEN_LVDSRX1_V_ACTIVE_MIN_ERR 0x0110	//h[3]
#define BU18TL82_IEN_LVDSRX1_H_TOTAL_MAX_ERR 0x0110		//h[4]
#define BU18TL82_IEN_LVDSRX1_H_TOTAL_MIN_ERR 0x0110		//h[5]
#define BU18TL82_IEN_LVDSRX1_H_ACTIVE_MAX_ERR 0x0110	//h[6]
#define BU18TL82_IEN_LVDSRX1_H_ACTIVE_MIN_ERR 0x0110	//h[7]
#define BU18TL82_IEN_IO_STUCK_GPIO0 0x0111	//h[0]
#define BU18TL82_IEN_IO_STUCK_GPIO1 0x0111	//h[1]
#define BU18TL82_IEN_IO_STUCK_GPIO2 0x0111	//h[2]
#define BU18TL82_IEN_IO_STUCK_GPIO3 0x0111	//h[3]
#define BU18TL82_IEN_IO_STUCK_GPIO4 0x0111	//h[4]
#define BU18TL82_IEN_IO_STUCK_GPIO5 0x0111	//h[5]
#define BU18TL82_IEN_IO_STUCK_GPIO6 0x0111	//h[6]
#define BU18TL82_IEN_IO_STUCK_GPIO7 0x0111	//h[7]
#define BU18TL82_IEN_IO_STUCK_IRQ 0x0112	//h[1]
#define BU18TL82_IEN_IDS_UNSTABLE 0x0112	//h [7] 1’b0
#define BU18TL82_IEN_I2C_A_TIMEOUT 0x0113	//h [0] 1’b0
#define BU18TL82_IEN_I2C_A_XMIT_ERR 0x0113	//h [1] 1’b0
#define BU18TL82_IEN_I2C_B_TIMEOUT 0x0114	//h [0] 1’b0
#define BU18TL82_IEN_I2C_B_XMIT_ERR 0x0114	//h [1] 1’b0
#define BU18TL82_IEN_REGCRC_ERR_PAGE0 0x0115	//h[0]
#define BU18TL82_IEN_REGCRC_ERR_PAGE1 0x0115	//h[1]
#define BU18TL82_IEN_REGCRC_ERR_PAGE2 0x0115	//h[2]
#define BU18TL82_IEN_REGCRC_ERR_PAGE3 0x0115	//h[3]
#define BU18TL82_IEN_REGCRC_ERR_PAGE4 0x0115	//h[4]
#define BU18TL82_IEN_REGCRC_ERR_PAGE5 0x0115	//h[5]
#define BU18TL82_IEN_CLKDETECT_CLKIN0_STOP 0x0116	//h [0] 1’b0
#define BU18TL82_IEN_CLKDETECT_CLKIN0_UNLOCK 0x0116	//h [1] 1’b0
#define BU18TL82_IEN_CLKDETECT_OSC_STOP 0x0116		//h [4] 1’b0
#define BU18TL82_IEN_CLKDETECT_OSC_UNLOCK 0x0116	//h [5] 1’b0
#define BU18TL82_IEN_CLKDETECT_CLKIN1_STOP 0x0117	//h [0] 1’b0
#define BU18TL82_IEN_CLKDETECT_CLKIN1_UNLOCK 0x0117	//h [1] 1’b0
#define BU18TL82_IEN_CLKDETECT_LVDSRX0_STOP 0x0118		//h [0] 1’b0
#define BU18TL82_IEN_CLKDETECT_LVDSRX0_UNLOCK 0x0118	//h [1] 1’b0
#define BU18TL82_IEN_CLKDETECT_MIPIRX0_STOP 0x0118		//h [4] 1’b0
#define BU18TL82_IEN_CLKDETECT_MIPIRX0_UNLOCK 0x0118	//h [5] 1’b0
#define BU18TL82_IEN_CLKDETECT_LVDSRX1_STOP 0x0119		//h [0] 1’b0
#define BU18TL82_IEN_CLKDETECT_LVDSRX1_UNLOCK 0x0119	//h [1] 1’b0
#define BU18TL82_IEN_CLKDETECT_MIPIRX1_STOP 0x0119		//h [4] 1’b0
#define BU18TL82_IEN_CLKDETECT_MIPIRX1_UNLOCK 0x0119	//h [5] 1’b0
#define BU18TL82_IEN_CLKDETECT_CLLTX0_SCLK_STOP 0x011A		//h [0] 1’b0
#define BU18TL82_IEN_CLKDETECT_CLLTX0_SCLK_UNLOCK 0x011A	//h [1] 1’b0
#define BU18TL82_IEN_CLKDETECT_CLLTX0_PLLREF_STOP 0x011A	//h [4] 1’b0
#define BU18TL82_IEN_CLKDETECT_CLLTX0_PLLREF_UNLOCK 0x011A	//h [5] 1’b0
#define BU18TL82_IEN_CLKDETECT_CLLTX1_SCLK_STOP 0x011B		//h [0] 1’b0
#define BU18TL82_IEN_CLKDETECT_CLLTX1_SCLK_UNLOCK 0x011B	//h [1] 1’b0
#define BU18TL82_IEN_CLKDETECT_CLLTX1_PLLREF_STOP 0x011B	//h [4] 1’b0
#define BU18TL82_IEN_CLKDETECT_CLLTX1_PLLREF_UNLOCK 0x011B	//h [5] 1’b0
#define BU18TL82_IEN_STATUS_RX0_ISR00 0x0121	//h [0] 1’b0
#define BU18TL82_IEN_STATUS_RX0_ISR01 0x0121	//h [1] 1’b0
#define BU18TL82_IEN_STATUS_RX0_ISR02 0x0121	//h [2] 1’b0
#define BU18TL82_IEN_STATUS_RX0_ISR03 0x0121	//h [3] 1’b0
#define BU18TL82_IEN_STATUS_RX0_ISR04 0x0121	//h [4] 1’b0
#define BU18TL82_IEN_STATUS_RX0_ISR05 0x0121	//h [5] 1’b0
#define BU18TL82_IEN_STATUS_RX0_ISR06 0x0121	//h [6] 1’b0
#define BU18TL82_IEN_STATUS_RX0_ISR07 0x0121	//h [7] 1’b0
#define BU18TL82_IEN_STATUS_RX0_ISR08 0x0122	//h [0] 1’b0
#define BU18TL82_IEN_STATUS_RX0_ISR09 0x0122	//h [1] 1’b0
#define BU18TL82_IEN_STATUS_RX0_ISR10 0x0122	//h [2] 1’b0


struct bu18tl82_gpio_sw_reg {
	unsigned int reg;
	unsigned int mask;	//2/4/6/8ma
};

struct bu18tl82_gpio_oen_reg {
	unsigned int reg;
	unsigned int mask;	//0:output 1:input
};

struct bu18tl82_gpio_pden_reg {
	unsigned int reg;
	unsigned int mask;	//0:no pulldown 1:connect pulldown
};

struct bu18tl82_gpio_id_low_reg {
	unsigned int reg;
	unsigned int mask;	//b2b1b0
};

struct bu18tl82_gpio_id_high_reg {
	unsigned int reg;
	unsigned int mask;	//b11b10b9b8b7b6b5b4b3
};

static const struct bu18tl82_gpio_sw_reg bu18tl82_gpio_sw[8] = {
	{BU18TL82_IO_SW_GPIO0, BIT(2) | BIT(1)},
	{BU18TL82_IO_SW_GPIO1, BIT(2) | BIT(1)},
	{BU18TL82_IO_SW_GPIO2, BIT(2) | BIT(1)},
	{BU18TL82_IO_SW_GPIO3, BIT(2) | BIT(1)},
	{BU18TL82_IO_SW_GPIO4, BIT(2) | BIT(1)},
	{BU18TL82_IO_SW_GPIO5, BIT(2) | BIT(1)},
	{BU18TL82_IO_SW_GPIO6, BIT(2) | BIT(1)},
	{BU18TL82_IO_SW_GPIO7, BIT(2) | BIT(1)},
};

static const struct bu18tl82_gpio_oen_reg bu18tl82_gpio_oen[8] = {
	{BU18TL82_IO_OEN_GPIO0, BIT(3)},
	{BU18TL82_IO_OEN_GPIO1, BIT(3)},
	{BU18TL82_IO_OEN_GPIO2, BIT(3)},
	{BU18TL82_IO_OEN_GPIO3, BIT(3)},
	{BU18TL82_IO_OEN_GPIO4, BIT(3)},
	{BU18TL82_IO_OEN_GPIO5, BIT(3)},
	{BU18TL82_IO_OEN_GPIO6, BIT(3)},
	{BU18TL82_IO_OEN_GPIO7, BIT(3)},
};

static const struct bu18tl82_gpio_pden_reg bu18tl82_gpio_pden[8] = {
	{BU18TL82_IO_PDEN_GPIO0, BIT(4)},
	{BU18TL82_IO_PDEN_GPIO1, BIT(4)},
	{BU18TL82_IO_PDEN_GPIO2, BIT(4)},
	{BU18TL82_IO_PDEN_GPIO3, BIT(4)},
	{BU18TL82_IO_PDEN_GPIO4, BIT(4)},
	{BU18TL82_IO_PDEN_GPIO5, BIT(4)},
	{BU18TL82_IO_PDEN_GPIO6, BIT(4)},
	{BU18TL82_IO_PDEN_GPIO7, BIT(4)},
};

static const struct bu18tl82_gpio_id_low_reg bu18tl82_gpio_id_low[8] = {
	{BU18TL82_GPIO_SEL0_LOW, GENMASK(7, 0)},
	{BU18TL82_GPIO_SEL1_LOW, GENMASK(7, 0)},
	{BU18TL82_GPIO_SEL2_LOW, GENMASK(7, 0)},
	{BU18TL82_GPIO_SEL3_LOW, GENMASK(7, 0)},
	{BU18TL82_GPIO_SEL4_LOW, GENMASK(7, 0)},
	{BU18TL82_GPIO_SEL5_LOW, GENMASK(7, 0)},
	{BU18TL82_GPIO_SEL6_LOW, GENMASK(7, 0)},
	{BU18TL82_GPIO_SEL7_LOW, GENMASK(7, 0)},
};

static const struct bu18tl82_gpio_id_high_reg bu18tl82_gpio_id_high[8] = {
	{BU18TL82_GPIO_SEL0_HIGH, GENMASK(2, 0)},
	{BU18TL82_GPIO_SEL1_HIGH, GENMASK(2, 0)},
	{BU18TL82_GPIO_SEL2_HIGH, GENMASK(2, 0)},
	{BU18TL82_GPIO_SEL3_HIGH, GENMASK(2, 0)},
	{BU18TL82_GPIO_SEL4_HIGH, GENMASK(2, 0)},
	{BU18TL82_GPIO_SEL5_HIGH, GENMASK(2, 0)},
	{BU18TL82_GPIO_SEL6_HIGH, GENMASK(2, 0)},
	{BU18TL82_GPIO_SEL7_HIGH, GENMASK(2, 0)},
};

struct bu18tl82_ien_reg {
	unsigned int reg;
	unsigned int ien;
};

struct bu18tl82_isr_reg {
	unsigned int reg;
	unsigned int isr;
};

static const struct bu18tl82_ien_reg bu18tl82_reg_ien[21] = {
	{BU18TL82_IEN_BCCRX0_STATUS_NEAR_LOST, BIT(3) | BIT(7)},
	{BU18TL82_IEN_BCCRX1_STATUS_NEAR_LOST, BIT(3) | BIT(7)},

	{BU18TL82_IEN_MIPIRX0_SOT_ERR, BIT(0) | BIT(0) | BIT(2)},
	{BU18TL82_IEN_MIPIRX0_ECC1BIT_ERR, BIT(0) | BIT(0) | BIT(2)},

	{BU18TL82_IEN_MIPIRX1_SOT_ERR, BIT(0) | BIT(0) | BIT(2)},
	{BU18TL82_IEN_MIPIRX1_ECC1BIT_ERR, BIT(0) | BIT(0) | BIT(2)},

	{BU18TL82_IEN_LVDSRX0_V_TOTAL_MAX_ERR, 0XFF},
	{BU18TL82_IEN_LVDSRX1_V_TOTAL_MAX_ERR, 0XFF},

	{BU18TL82_IEN_IO_STUCK_GPIO0, 0XFF},
	{BU18TL82_IEN_IO_STUCK_IRQ, BIT(1) | BIT(7)},
	{BU18TL82_IEN_I2C_A_TIMEOUT, BIT(0) | BIT(1)},
	{BU18TL82_IEN_I2C_B_TIMEOUT, BIT(0) | BIT(1)},

	{BU18TL82_IEN_REGCRC_ERR_PAGE0, 0x3F},

	{BU18TL82_IEN_CLKDETECT_CLKIN0_STOP, BIT(0) | BIT(1) | BIT(4) | BIT(5)},
	{BU18TL82_IEN_CLKDETECT_CLKIN1_STOP, BIT(0) | BIT(1)},

	{BU18TL82_IEN_CLKDETECT_LVDSRX0_STOP, BIT(0) | BIT(1) | BIT(4) | BIT(5)},
	{BU18TL82_IEN_CLKDETECT_LVDSRX1_STOP, BIT(0) | BIT(1) | BIT(4) | BIT(5)},
	{BU18TL82_IEN_CLKDETECT_CLLTX0_SCLK_STOP, BIT(0) | BIT(1) | BIT(4) | BIT(5)},
	{BU18TL82_IEN_CLKDETECT_CLLTX1_SCLK_STOP, BIT(0) | BIT(1) | BIT(4) | BIT(5)},

	{BU18TL82_IEN_STATUS_RX0_ISR00, 0xff},
	{BU18TL82_IEN_STATUS_RX0_ISR08, BIT(0) | BIT(1) | BIT(2)},
};

static const struct bu18tl82_isr_reg bu18tl82_reg_isr[21] = {
	{BU18TL82_ISR_BCCRX0_STATUS_NEAR_LOST, BIT(3) | BIT(7)},
	{BU18TL82_ISR_BCCRX1_STATUS_NEAR_LOST, BIT(3) | BIT(7)},

	{BU18TL82_ISR_MIPIRX0_SOT_ERR, BIT(0) | BIT(0) | BIT(2)},
	{BU18TL82_ISR_MIPIRX0_ECC1BIT_ERR, BIT(0) | BIT(0) | BIT(2)},

	{BU18TL82_ISR_MIPIRX1_SOT_ERR, BIT(0) | BIT(0) | BIT(2)},
	{BU18TL82_ISR_MIPIRX1_ECC1BIT_ERR, BIT(0) | BIT(0) | BIT(2)},

	{BU18TL82_ISR_LVDSRX0_V_TOTAL_MAX_ERR, 0XFF},
	{BU18TL82_ISR_LVDSRX1_V_TOTAL_MAX_ERR, 0XFF},

	{BU18TL82_ISR_IO_STUCK_GPIO0, 0XFF},
	{BU18TL82_ISR_IO_STUCK_IRQ, BIT(1) | BIT(7)},
	{BU18TL82_ISR_I2C_A_TIMEOUT, BIT(0) | BIT(1)},
	{BU18TL82_ISR_I2C_B_TIMEOUT, BIT(0) | BIT(1)},

	{BU18TL82_ISR_REGCRC_ERR_PAGE0, 0x3F},

	{BU18TL82_ISR_CLKDETECT_CLKIN0_STOP, BIT(0) | BIT(1) | BIT(4) | BIT(5)},
	{BU18TL82_ISR_CLKDETECT_CLKIN1_STOP, BIT(0) | BIT(1)},

	{BU18TL82_ISR_CLKDETECT_LVDSRX0_STOP, BIT(0) | BIT(1) | BIT(4) | BIT(5)},
	{BU18TL82_ISR_CLKDETECT_LVDSRX1_STOP, BIT(0) | BIT(1) | BIT(4) | BIT(5)},
	{BU18TL82_ISR_CLKDETECT_CLLTX0_SCLK_STOP, BIT(0) | BIT(1) | BIT(4) | BIT(5)},
	{BU18TL82_ISR_CLKDETECT_CLLTX1_SCLK_STOP, BIT(0) | BIT(1) | BIT(4) | BIT(5)},

	{BU18TL82_ISR_STATUS_RX0_ISR00, 0xff},
	{BU18TL82_ISR_STATUS_RX0_ISR08, BIT(0) | BIT(1) | BIT(2)},
};

#endif
